1. Field of the Invention
This invention relates to integrated circuit (IC) diagnosis, characterization and modification using charged particle beams.
2. Background
Electrical Failure Analysis isolates electrical issues in complete IC devices running under test (DUT). Shrinking nodes, new materials, and more complex structures are driving new isolation technologies and improvement of system resolution to detect the faults.
Electron beam diagnostic systems are a powerful tool used for IC characterization and debugging applications. Electron beam diagnostic systems are used, for example, for secondary electron imaging, circuit navigation using a built-in computer automated design (CAD) display, and voltage measurements from active circuits using voltage contrast principles. (See, for example, U.S. Pat. No. 4,706,019.) Other electron beams diagnostic systems use the electrons in the beam to affect a signal to detect faults. Such systems include Electron Beam-Induced Current (EBIC), Resistive Contrast Imaging (RCI), biased RCI (BRCI), Charge-Induced Voltage Alteration (CIVA), Low Energy CIVA (LECIVA), Electron-Beam Absorbed Current (EBAC), and Electron Beam-Induced Resistance Change (EBIRCH).
U.S. Pat. No. 6,872,581 to Shaw, et al., teaches methods for IC diagnosis, characterization, or modification using a charged particle beam. In one implementation, the bulk silicon substrate of an IC is thinned from the back side to about 1 to 3 μm from the deepest well, and a voltage is applied to a circuit element that is beneath the surface of the thinned substrate. The applied voltage induces an electrical potential on the surface, which is detected by the interaction of the induced voltage with the charged particle beam. U.S. Pat. No. 5,972,725 to Wollesen, et al., similarly enables back-side voltage measurement by removing a portion of the silicon substrate using a combination of mechanical polishing and plasma etching, providing a supply voltage to the circuit, and observing the voltage contrast in the electron beam image.
It is desirable for such examination techniques to activate the IC circuitry with test signals design to operate the IC in test conditions. Activating modern ICs inside an SEM chamber requires hundreds to thousands of high-speed electrical feedthroughs, and this is a challenge. The number of high-speed feedthroughs required generally increases as the size (transistor count) and complexity of circuits generally accompanies an increased count in input output (I/O) terminals on the device. Historical e-beam solutions all relied on electrical signals being “passed through” into a vacuum chamber of the SEM, which is a cumbersome and slow process that may require specialized connection equipment to be produced for a particular IC.